Intel (INTC)’s high-NA EUV lithography represents a significant leap forward in semiconductor manufacturing technology, poised to dominate over traditional EUV systems. This advanced technology employs an increased numerical aperture of 0.55, compared to 0.33 in current EUV systems, enabling the production of even smaller and more intricate features on silicon wafers. The higher numerical aperture allows for sharper imaging and improved resolution, pushing the boundaries of chip manufacturing into the angstrom era.
Intel has secured a crucial first-mover advantage by acquiring ASML’s entire 2024 stock of High-NA EUV machines. This strategic move includes five to six units, each valued at approximately $370 million, with the first machine already delivered and assembled at Intel’s Oregon facility in early 2024. By monopolizing the initial production run of these cutting-edge tools, Intel has positioned itself at the forefront of semiconductor technology advancement. This aggressive acquisition strategy provides Intel with several key advantages:
- Technological leadership: Intel will be the first to integrate High-NA EUV into its manufacturing processes, potentially leapfrogging competitors in transistor density and chip performance.
- Process optimization: Early access allows Intel to refine its manufacturing techniques and overcome initial challenges before competitors even receive their machines.
- Attracting partnerships: Intel’s advanced capabilities may draw high-profile customers like Microsoft and potentially Nvidia to its foundry services.
- Market positioning: This move could help Intel reverse its recent foundry business losses and reclaim its position as a leading semiconductor manufacturer.
- Ecosystem development: Intel can start building the necessary infrastructure and expertise around High-NA EUV technology, creating a significant barrier to entry for latecomers.
With competitors like Samsung and SK Hynix potentially waiting until the second half of 2025 for their High-NA EUV equipment, Intel has secured a critical time advantage in the race to develop and commercialize next-generation semiconductor technologies. This head start could translate into a substantial competitive edge in the rapidly evolving chip industry, potentially reshaping the semiconductor landscape in Intel’s favor.
Intel lost out on this cycle of silicon because TSCM had bought up all the ASML EUV machine 5-7 years ago.
Now, that Intel has secured NA-EUV machines, it’s in a much strong position for the next silicon cycle
EUV
It’s important to note that while TSMC currently leads in EUV-based chip manufacturing, companies like Samsung and Intel are working hard to catch up. Intel, for example, has made significant investments in R&D and has secured early access to ASML’s next-generation High NA EUV machines in an attempt to regain technological leadership.
TSMC currently utilizes Extreme Ultraviolet (EUV) lithography for its advanced semiconductor nodes. As of now, TSMC’s most advanced node in production using EUV is the 3nm (N3) process. This node features up to 25 EUV layers, with some layers using EUV double-patterning to achieve higher logic and SRAM transistor density compared to the previous 5nm node. TSMC has also detailed its roadmap for future nodes, including the 2nm (N2) process expected around 2025, and the 1.4nm node anticipated around 2028. The 1nm node is projected to be introduced around 2031. However, these future nodes may require the adoption of High-NA EUV tools, which TSMC plans to adopt by 2030. In summary, TSMC’s current EUV capabilities allow for the production of 3nm nodes, with plans to advance to smaller nodes in the coming years.
NA-EUV
High-NA EUV (High Numerical Aperture Extreme Ultraviolet) lithography is the next generation of semiconductor manufacturing technology designed to enable the production of even smaller and more densely packed transistors on computer chips.Key points about High-NA EUV:
- Improved resolution: High-NA EUV increases the numerical aperture from 0.33 in current EUV systems to 0.55, allowing for sharper imaging and smaller feature sizes.
- Smaller transistors: It enables chipmakers to print transistors 1.7 times smaller and achieve transistor densities 2.9 times higher than current EUV systems.
- Anamorphic optics: High-NA EUV uses an innovative anamorphic optical design that demagnifies the pattern by 4x in one direction and 8x in the other, allowing for better resolution while maintaining compatibility with existing reticle sizes.
High-NA EUV lithography offers several advantages over traditional EUV lithography, primarily in terms of resolution, process complexity, and cost-effectiveness. Here are the key reasons why High-NA EUV is considered better:
Lower Edge Placement Error
- High-NA EUV reduces the cumulative edge placement error associated with mask splits in multi-patterning processes. This improvement leads to better alignment and higher fidelity in the final patterns, which is critical for advanced nodes.
Enhanced Design Flexibility
- The improved imaging window of High-NA EUV allows for more complex design elements to be implemented on a single mask. This flexibility is beneficial for designing advanced semiconductor devices with intricate features.
Higher Yield
- By reducing the number of processing steps required, High-NA EUV can improve yield. Fewer steps mean fewer opportunities for defects to be introduced, which is essential for maintaining high production yields at advanced nodes Lower Edge Placement Error.
NA-EUV and AI
Angstrom-scale chip design represents a significant advancement in semiconductor technology that could potentially facilitate running local large language models (LLMs) on smartphones. Here’s how angstrom chips could enable this:
- Increased transistor density: Angstrom-scale processes allow for even more transistors to be packed onto a single chip compared to nanometer-scale designs. This increased density enables more powerful and efficient processors that can handle the computational demands of LLMs.
- Improved power efficiency: With advanced transistor structures like gate-all-around (GAA), angstrom-scale chips can achieve better power efficiency. This is crucial for running resource-intensive LLMs on battery-powered devices like smartphones.
- Enhanced memory scaling: GAA structures may allow for better memory scaling compared to current designs. This could provide the necessary memory capacity and bandwidth required to run LLMs locally on mobile devices.
- Backside power distribution: This technique, which moves power distribution under the transistors, frees up more space for signal routing. This can lead to better overall chip performance and efficiency, which is essential for running complex AI models on mobile devices.
- Multi-die systems: Angstrom-scale processes can be combined with multi-die system designs, allowing for more specialized and efficient chips that could be optimized for AI workloads like LLMs.
While angstrom-scale chips are still in development and not yet commercially available, some smartphone manufacturers are already working on incorporating LLMs into their devices. Chinese companies like Huawei and Xiaomi are reportedly integrating LLMs into their smartphones. This trend suggests that as chip technology advances, we may see more powerful and efficient processors capable of running increasingly sophisticated LLMs locally on mobile devices.
Intel may be the foundry to print the chips needed for Iphone and Android LLM in 2027
INTC’s Bear Thesis
Intel has had a rough month. If you browse the online forums you will see numerous threads about how Intel’s most recent line of chips frequently throw errors and cause numerous problems in applications. This issue has also received decent attention in the press and it effects their entire line of most recent chips, including the commercial sector and server consumers; this issue is not limited to retail consumers. Intel’s response to these reports has been a bit schizo; first denying the problem exists, then claiming they found the issue and had a fix lined up, then announcing there was no possible fix and most recently denying that there would be a recall despite the faults in their product. This behavior has had a negative impact on consumer sentiment for the company.
Recently in the news Intel has announced mass layoffs, this is not a good look as a company enters earnings. If Earnings were good we wouldn’t expect an announcement of mass layoffs, it is another bearish indicator as Intel enters earnings after market closes today.
Looking a little deeper into the most recent earnings report and comparing them with google’s stock graph over the year, you can see that with the last two earnings reports INTC dropped immediately following earnings. The last earnings report drop is the most interesting to me since even though Intel reported a slight beat in earnings, the stock dropped over 10% the next day. I believe the earnings report coming tonight will be very bad for Intel and we will see a similar drop in stock price to what occurred the previous 2 earnings as past behavior is the best indicator of future behavior.
Counter-thesis: I’m not overly confident in this play. INTC has dropped around 4% over the last week. It’s possible that investors have already “priced in” the expected bad numbers into the upcoming earnings; if so while the earnings report will definitely be bad regardless, they may beat the expected terrible earnings with mere bad numbers and the stock may stay flat or even rise slightly; this is especially true since investors are aware of mass layoffs which will reduce expected costs for the upcoming quarter.